1. Field of the Disclosure
Generally, the present disclosure relates to the field of integrated circuits including memory devices and, more particularly, to integrated circuits including nonvolatile memory.
2. Description of the Related Art
Nonvolatile memory such as, for example, flash memory, may be used in various storage devices such as, for example, secure digital memory cards (SD cards), USB sticks, solid state drives (SSDs) and internal memory of various electronic devices such as, for example, mobile phones, tablet computers, media players, etc. Other applications of nonvolatile memory include embedded systems, wherein nonvolatile memory is provided in addition to logic circuits and/or volatile memory such as static random access memory (SRAM) and/or dynamic random access memory (DRAM) and wherein the nonvolatile memory, the logic circuits and the volatile memory are physically and electrically integrated on a single substrate, for example, a single monolithic silicon substrate. Embedded systems including nonvolatile memory find applications in various fields such as, for example, in automotive, industry and communication market segments. Integrating nonvolatile memory, logic circuitry and volatile memory on a single substrate may help to improve performance and reduce costs compared to solutions wherein nonvolatile memory and logic circuitry are provided on separate substrates, for example, due to an elimination of input/output buffers, design flexibility, lower power consumption and/or system-on-a-chip capability.
Examples of a nonvolatile memory cell of nonvolatile memory may include a source region and a drain region that are formed in a semiconductor material. Between the source region and the drain region, a channel region is provided that is doped differently than the source region and the drain region. Over the channel region, a floating gate and a select gate are provided. Over the floating gate, a control gate is provided, and an erase gate is provided over the source region. The select gate, the floating gate, the control gate and the erase gate are electrically insulated from each other and from the source, drain and channel regions by electrically insulating materials. The floating gate may be surrounded by electrically insulating material so that it is electrically floating. The source region, the drain region, the select gate, the control gate and the erase gate may have respective electrical contacts connected thereto so that voltages may be applied to the source region, the drain region and the select, control and erase gates for performing operations of programming, erasing and reading the nonvolatile memory cell.
For programming the nonvolatile memory cell, voltages adapted for creating a relatively strong, substantially vertically oriented electrical field in the channel region between the select gate and the floating gate and a current providing electrons to the channel region may be applied to the select and control gates and the source and drain regions, which may cause a hot electron injection into the floating gate so that the floating gate is electrically charged. The electric charge of the floating gate may, in particular, depend on the voltage applied to the drain region. Since the floating gate is electrically floating, the charge injected into the floating gate may remain in the floating gate and may create an electric field that acts on a portion of the channel region below the floating gate.
For reading data from the nonvolatile memory cell, a voltage may be applied between the source region and the drain region, and a voltage adapted for creating an electrically conductive channel below the select gate may be applied to the select gate. Due to the influence of the electric charge in the floating gate on the portion of the channel region below the floating gate, a conductivity of the channel region and a current flowing between the source region and the drain region may be influenced by the electric charge on the floating gate. Thus, it may be determined if an electric charge has been injected into the floating gate by means of a programming operation.
For erasing the nonvolatile memory cell, a relatively high positive voltage may be applied to the erase gate so that a Fowler-Nordheim tunneling of electrons from the floating gate to the erase gate may be obtained. Thus, an electric charge injected into the floating gate in the programming of the nonvolatile memory cell may be removed from the floating gate.
Integrating nonvolatile memory cells as described above and field effect transistors which may be used, for example, in logic circuits and/or static random access memory cells may have some issues associated therewith, in particular when the field effect transistors are provided in accordance with high-k metal gate technology. Field effect transistors provided in accordance with high-k metal gate technology may include a gate structure including a gate insulation layer that is formed of a high-k dielectric material having a greater dielectric constant than silicon dioxide, such as, for example, hafnium dioxide, and a gate electrode including a metal such as, for example, lanthanum, lanthanum nitride, titanium nitride, aluminum and/or aluminum nitride. In particular, when high-k metal gate field effect transistors are formed in accordance with a gate-first approach, wherein the gate structures of the field effect transistors are formed before ion implantation processes are performed for forming source and drain regions of the field effect transistors, integration issues may occur since gate stacks that are used for some or all of the gates of the nonvolatile memory cells are different from those used for forming the gate structures of the high-k metal gate field effect transistors. Moreover, there may be integration issues when the gates of the nonvolatile memory cells are patterned subsequently and conventional patterning is performed in parts of the integrated circuit that include logic circuits and/or static random access memory.
Moreover, due to the presence of multiple gates, nonvolatile memory cells as described above may require a relatively large area on a substrate on which an integrated circuit wherein the nonvolatile memory cells are provided is formed.
The present disclosure provides semiconductor structures and methods for the formation of semiconductor structures which may help to substantially overcome or at least reduce some or all of the above-mentioned issues.